Combinational Full Adder¶
Verilog Code¶
RST Directive¶
1 2 3 | .. no-license:: ../code/verilog/adder.v
:language: verilog
:linenos:
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Result¶
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 | module ADDER (
a, b, cin,
sum, cout
);
input wire a;
input wire b;
input wire cin;
output wire sum;
output wire cout;
// Full adder combinational logic
assign sum = a ^ b ^ cin;
assign cout = ((a ^ b) & cin) | (a & b);
endmodule
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Yosys BlackBox Diagram¶
RST Directive¶
1 2 3 | .. hdl-diagram:: ../code/verilog/adder.v
:type: yosys-bb
:module: ADDER
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