Combinational Full Adder
========================

Verilog Code
++++++++++++

RST Directive
*************

.. code-block:: rst
   :linenos:

   .. no-license:: ../code/verilog/adder.v
      :language: verilog
      :linenos:


Result
******

.. no-license:: ../code/verilog/adder.v
   :language: verilog
   :linenos:


Yosys BlackBox Diagram
++++++++++++++++++++++

RST Directive
*************

.. code-block:: rst
   :linenos:
   :emphasize-lines: 2

   .. hdl-diagram:: ../code/verilog/adder.v
      :type: yosys-bb
      :module: ADDER

Result
******

.. hdl-diagram:: ../code/verilog/adder.v
   :type: yosys-bb
   :module: ADDER


Yosys AIG Diagram
+++++++++++++++++

RST Directive
*************

.. code-block:: rst
   :linenos:
   :emphasize-lines: 2

   .. hdl-diagram:: ../code/verilog/adder.v
      :type: yosys-aig
      :module: ADDER

Result
******

.. hdl-diagram:: ../code/verilog/adder.v
   :type: yosys-aig
   :module: ADDER


NetlistSVG Diagram
++++++++++++++++++

RST Directive
*************

.. code-block:: rst
   :linenos:
   :emphasize-lines: 2

   .. hdl-diagram:: ../code/verilog/adder.v
      :type: netlistsvg
      :module: ADDER


Result
******

.. hdl-diagram:: ../code/verilog/adder.v
   :type: netlistsvg
   :module: ADDER