CARRY4 example for Series 7 FPGA¶
CARRY4 defined directly¶
19 20 21 22 23 24 25 | module CARRY4(output [3:0] CO, O, input CI, CYINIT, input [3:0] DI, S);
assign O = S ^ {CO[2:0], CI | CYINIT};
assign CO[0] = S[0] ? CI | CYINIT : DI[0];
assign CO[1] = S[1] ? CO[0] : DI[1];
assign CO[2] = S[2] ? CO[1] : DI[2];
assign CO[3] = S[3] ? CO[2] : DI[3];
endmodule
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1 2 3 | .. hdl-diagram:: ../code/verilog/carry4-whole.v
:type: netlistsvg
:module: CARRY4
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CARRY4 defined by components¶
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 | `include "muxcy.v"
`include "xorcy.v"
module CARRY4(output [3:0] CO, O, input CI, CYINIT, input [3:0] DI, S);
wire CIN = CI | CYINIT;
MUXCY muxcy0 (.O(CO[0]), .CI(CIN), .DI(DI[0]), .S(S[0]));
MUXCY muxcy1 (.O(CO[1]), .CI(CO[0]), .DI(DI[1]), .S(S[1]));
MUXCY muxcy2 (.O(CO[2]), .CI(CO[1]), .DI(DI[2]), .S(S[2]));
MUXCY muxcy3 (.O(CO[3]), .CI(CO[2]), .DI(DI[3]), .S(S[3]));
XORCY xorcy0 (.O(O[0]), .CI(CIN), .LI(S[0]));
XORCY xorcy1 (.O(O[1]), .CI(CO[0]), .LI(S[1]));
XORCY xorcy2 (.O(O[2]), .CI(CO[1]), .LI(S[2]));
XORCY xorcy3 (.O(O[3]), .CI(CO[2]), .LI(S[3]));
endmodule
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19 20 21 | module MUXCY(output O, input CI, DI, S);
assign O = S ? CI : DI;
endmodule
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19 20 21 | module XORCY(output O, input CI, LI);
assign O = CI ^ LI;
endmodule
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MUXCY¶
1 2 3 4 | .. hdl-diagram:: ../code/verilog/muxcy.v
:type: netlistsvg
:caption: muxcy.v
:module: MUXCY
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XORCY¶
1 2 3 4 | .. hdl-diagram:: ../code/verilog/xorcy.v
:type: netlistsvg
:caption: xorcy.v
:module: XORCY
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CARRY4 without flatten¶
1 2 3 4 | .. hdl-diagram:: ../code/verilog/carry4-bits.v
:type: netlistsvg
:module: CARRY4
:caption: carry4-bits.v without flatten
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CARRY4 with flatten¶
1 2 3 4 5 | .. hdl-diagram:: ../code/verilog/carry4-bits.v
:type: netlistsvg
:module: CARRY4
:flatten:
:caption: carry4-bits.v with flatten
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